ALEVA

Engineering

Ultrasound ADC Clocks: Budget Jitter at the Input Frequency

A short engineering review of sampling-clock jitter, input-frequency dependence and traceable timing budgets for ultrasound OEM receivers, with explicitly hypothetical calculations and public references.

ALEVA · Updated October 18, 2026

ALEVA | California, USA

Engineering question: Does a higher sampling rate, by itself, solve timing-noise limits in an ultrasound receiver?

Start with the slope of the received signal

A small sampling-time error produces an amplitude error approximately equal to the input signal's instantaneous slope multiplied by that timing error. For a sinusoid and small, uncorrelated RMS timing jitter, the familiar jitter-only limit is SNR_j = -20 log10(2 pi f_in sigma_t). The frequency in this expression is the analog input frequency—not the sampling frequency. TI's 2010 tutorial derives this relationship; it is a fundamental reference, not a new device announcement.

As a reproducible illustration of the same equation presented in ADI's MT-007 tutorial, inserting sigma_t = 1 ps gives approximately 84.0 dB at 10 MHz and 78.0 dB at 20 MHz. These calculated values exclude thermal noise, quantization, distortion and other impairments. They are neither measured scanner performance nor ALEVA hardware specifications.

One RMS number is not the complete clock specification

Record the phase-noise integration band, clock distribution path and ADC aperture-jitter assumptions. Combine independent RMS contributions using root-sum-square only when independence and compatible measurement definitions are justified. Fixed channel skew is a different timing error and should have a separate acceptance check.

A peer-reviewed study by Kowalski and colleagues, published online in October 2025 and assigned to Measurement volume 258 (2026), characterizes ADC aperture phase noise in the frequency domain. Its two-channel measurement separates correlated and uncorrelated contributions. This is general ADC metrology—not validation of an ultrasound scanner or evidence that a particular clock meets a probe's requirements.

Make the OEM handover testable

Our proposed handover record specifies the receive band, sample rate, clock-noise integration limits, timing distribution and test configuration together. Compare candidate clocks with the same ADC, input amplitude and receive settings; assess the complete receiver rather than the oscillator specification alone. A lower-jitter clock may add power, cost or routing constraints without a useful system improvement if another noise source dominates. Conversely, higher sample rate or downstream IQ decimation does not, by itself, remove timing error already introduced at acquisition.

This is an engineering analysis and proposed verification practice, not a claim of ALEVA implementation, clinical benefit or regulatory approval. For related system boundaries, see ALEVA's transmit/receive interface guide.

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