FPGA + GPU ultrasound beamformer engineering
ALEVA Technologies Inc. (ALEVA), based in California, USA, provides project-scoped OEM ultrasound beamformer engineering, including FPGA/GPU processing and probe integration. Board supply or technology transfer is defined in the agreed project scope.
64/64 · 128/128 · 256/256 channels — plus a 32/64 handheld class.
Two engines, one real-time image chain
Specify the FPGA/GPU boundary for the required acquisition and output. Processing near acquisition can reduce downstream traffic, but record which channel information remains available. Sending channel data to a GPU preserves different reconstruction options and changes transport, memory and host requirements. Evaluate the complete pipeline; processor labels do not establish real-time performance.
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FPGA receive beamforming
Deterministic, low-latency processing in hardware — not a general-purpose CPU.
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GPU reconstruction & AI
Plane-wave/ultrafast reconstruction, advanced modes and AI, in software.
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Design, build & supply
We manufacture and deliver production beamformer boards, not just designs.
Built at the scale your probe needs
Transmit / receive channel classes, matched to the probe and clinical target.
| Class | Transmit / Receive channels | Typical use |
|---|---|---|
| Standard | 64 / 64 | Compact systems, point-of-care carts |
| Mid-range | 128 / 128 | General imaging, higher line density |
| High-end | 256 / 256 | Premium imaging, high frame rates, research |
| Handheld / portable | 32 / 64 | Handheld POCUS — latest Texas Instruments ICs |
The handheld class reaches a compact 32/64 configuration within the power and thermal envelope a portable device demands — without giving up image quality.
What’s inside
Analog front end
Low-noise amplification, TGC and high-speed ADCs feeding the FPGA.
Parallel receive processing
Multiple simultaneous receive beams for high frame rates and ultrafast modes.
Latest TI front-end silicon
Modern Texas Instruments AFEs and data converters, especially in the handheld line.
Raw RF / channel data
On research configurations, tap pre-beamformed RF data for custom algorithms and AI.
Imaging modes
B-mode, M-mode, color/power/spectral Doppler, strain & shear-wave elastography, plane-wave and ultrafast.
OEM-matched
Tuned to your probe and clinical target, not a generic board you design around.
Because we own the whole receive chain — front end, beamformer and image pipeline — we tune the parts together, which is exactly where real image quality comes from. Read more about our OEM ultrasound design & manufacturing program.
Two ways to put our beamformer in your system
It’s our platform — you choose how much of it you want to own.
OEM board supply
We manufacture and deliver production beamformer boards tuned to your probe and clinical target — you integrate them into your system, from prototype through volume.
Technology transfer
Take ownership of the platform: we transfer the design and the build know-how so your team can produce and evolve the beamformer in-house, with our engineering support alongside.
Frequently asked questions
What is a parallel-receive ultrasound beamformer?
A parallel-receive beamformer processes many receive lines at once instead of one at a time. That enables high channel counts, high frame rates and modern acquisition such as plane-wave and synthetic-aperture imaging — faster acquisition and better temporal resolution for moving structures like the heart and blood flow.
Why a hybrid FPGA + GPU beamformer?
The FPGA handles deterministic, low-latency receive beamforming in hardware, where timing and channel count matter most. The GPU handles reconstruction, advanced modes and AI-assisted imaging, where massive parallel compute pays off. The hybrid split stays real-time at high channel counts while remaining flexible enough to add new modes in software.
What channel counts (Tx/Rx) do you build?
System-class boards in 64/64, 128/128 and 256/256 transmit/receive channels, plus a 32/64 handheld class on the latest Texas Instruments ultrasound front-end ICs.
Can you build a handheld ultrasound beamformer?
Yes. Our 32/64 handheld class uses the latest Texas Instruments ICs to reach a compact configuration within the power and thermal envelope a handheld device requires, without giving up image quality.
Do you provide raw RF / channel-data access?
Yes — on our research configurations, partners and researchers can tap pre-beamformed raw RF / channel data for custom algorithms, new imaging methods and AI pipelines.
Is this your own beamformer, and can we license or own it?
Yes. It’s our own proprietary beamformer — we designed, developed and built it in-house; it isn’t a third-party board we resell. You can work with it two ways: buy production boards from us as an OEM, or take a full technology transfer in which we hand over the design and the build know-how so your team can manufacture and evolve it themselves.
Do you repair beamformer or engine boards?
This beamformer program covers design, development and board supply. Contact ALEVA to confirm whether a specific service request is in scope.
Need a beamformer matched to your probe?
Tell us your channel count, probe and imaging targets, and we’ll scope the board — from prototype to production supply.
Evaluate an ultrasound beamformer OEM proposal end to end
Requirements
Record active transmit and receive channels separately from element count. Define the acquisition sequence, sample representation, required RF/IQ/image output, metadata and calibration. Identify the probe, host, reconstruction workload and operating conditions against which the proposed configuration will be evaluated.
Verification evidence
Request acquisition-to-output measurements with defined timestamp boundaries, latency distribution, sustained throughput and capture-loss reporting. Record configuration revisions and test conditions so competing results are comparable. Include behavior during host stalls, buffer pressure and extended operation.
NVIDIA's CUDA guidance explains that overlapping transfers and computation depends on device capability and memory/stream setup. AMD's Vitis HLS documentation describes FIFO-depth investigation using co-simulation. These references support checking implementation conditions rather than inferring system performance from a processor name. CUDA 13.4, §10.1.2 · AMD UG1399, 2026.1.
Deliverables and handover
Separate the board-supply deliverables from any design-transfer package. Agree firmware and SDK interfaces, configuration records, production tests, maintenance and third-party dependencies. A technology-transfer proposal should identify the exact files, rights, build instructions and acceptance tests included; the label alone does not define what the receiving team can reproduce.
Discuss a beamformer evaluation · Compare architecture trade-offs.
FPGA GPU ultrasound beamformer architecture guide · Engine definition · Verification checklist
Share non-confidential requirements through our project contact page to discuss the agreed scope.